1. Field of the Invention
The present invention relates to a LSI device used for communication, and particularly to a LSI device used for communication based on a high speed serial bus.
2. Description of the Related Art
A kind of LSI device used for communication is well known which is defined in the xe2x80x9cIEEE Standard for a High Performance Serial Bus, IEEE Standard, 1394xe2x80x9d issued in 1995 by IEEE (Institute of Electrical and Electronic Engineers), and have been widely used.
The communication LSI device according to the IEEE Standard, 1394 has a control circuit called a physical layer circuit and is structured so as to receive control command signals through a link circuit corresponding to an external upper layer. In practical use of this communication LSI device in a host unit including a high speed serial bus, a plurality of LSI devices are used in correspondence with a plurality of serial buses which are usually included in the host unit. Therefore, the physical layer control circuit has a function to construct a tree connection (tree identifications (Ids) in the tree structure) of the plurality of LSI devices and to carry out configuration including allocation of identification numbers (self IDs) to individual LSI devices in the tree structure.
In general, in a product test process of semiconductor integrated circuits (LSI devices), a reliability test is carried out by use of a bias temperature screening method in which products are operated for a long time at a high temperature so that heat and electric stresses are applied to the products. Thus, initial failures are detected, so that the products having the initial failures are removed to obtain high reliability.
The bias temperature screening method is classified into a static bias temperature screening method and a dynamic bias temperature screening method. In the static bias temperature screening method, a non-operating LSI device is left under a high temperature condition in which only a power source voltage is supplied to the LSI devices. In this case, the circuit does not operate so that a part of the circuit does not receive electric stress. On the other hand, in the dynamic bias temperature screening method, a LSI device to be tested is left under a high temperature condition, and a signal pattern is externally supplied to the LSI device to operate the LSI device steadily. Thus, the test can be carried out in the state that heat and electric stresses are imposed to the LSI device. Therefore, the dynamic bias temperature screening method is much more effective among the bias temperature screening methods.
However, the test environment in which the dynamic bias temperature screening method is carried out needs to be constructed in a closed and limited space such as a constant temperature vessel. Hence, a device such as a pattern generator, which supplies a test pattern for the LSI device to be test, is difficult to be located in the test environment.
FIG. 1 is a block diagram showing the structure of a physical layer circuit 100 of a conventional communication LSI device. Referring to FIG. 1, the physical layer circuit 100 of the conventional communication LSI device is composed of a state machine 1, a timer 2, a link interface (I/F) circuit 3 and an inverter 4. The state machine 1 controls the entire operation of the communication LSI device. The timer 2 is used in the control of a state transit time of the state machine 1. The inverter 4 inverts a low active reset signal RB inputted from a reset terminal TR to output as a high active rest signal R.
The link interface circuit 3 functions as an interface to an external link circuit. The link interface circuit 3 inputs a command signal Q from the external link circuit through a command signal terminal TQ. The interface circuit 3 interprets the command signal Q and outputs an instruction IS to the state machine 1.
The state machine 1 receives a high active reset signal R and starts a predetermined configuration operation. Upon completion of the configuration operation, the state machine 1 outputs a high active flag signal F (called subaction gap) to the link interface circuit 3. An output from the timer 2 is supplied to the state machine 1, and the time of the configuration operation such as the time for the flag signal F to be outputted is controlled.
Next, operation of the physical layer circuit 100 of the conventional communication LSI device will be described with reference to FIG. 1 and FIGS. 2A to 2F. FIGS. 2A to 2F are timing charts showing waveforms at respective sections of the conventional physical layer circuit. At first, when the reset signal RB of a low level shown in FIG. 2A is inputted from the reset terminal TR, the reset signal R as the output of the inverter 4 is changed to a high level, as shown in FIG. 2D. At this time, the state machine 1 is reset to enter into an xe2x80x9cidlexe2x80x9d state. Thereafter, the reset signal R is changed to the low level when the reset terminal changes to the high level, and the reset state of the state machine 1 is released. Upon the release of the reset state, the state machine 1 starts a configuration operation as follows.
That is, in the configuration operation, under time control by the timer 2, the state S of the state machine 1 changes to a xe2x80x9cbus resetxe2x80x9d state, a xe2x80x9ctree IDxe2x80x9d state, a xe2x80x9cself IDxe2x80x9d state and the xe2x80x9cidlexe2x80x9d state, as shown in FIG. 2B. In the xe2x80x9cbus resetxe2x80x9d state, a serial bus as a connection target is initialized. In the xe2x80x9ctree IDxe2x80x9d state, a tree structure is constructed to include another communication LSI device in a device associated with the target serial bus. In the xe2x80x9cself IDxe2x80x9d state, identification numbers are allocated to the respective communication LSI devices in the tree structure. Then, the state S of the state machine 1 returns to the xe2x80x9cidlexe2x80x9d state. When the timer 2 counts a predetermined time after the return of the state machine 1 to the xe2x80x9cidlexe2x80x9d state, the state machine 1 then outputs a pulse of the high level as the flag signal F to end the configuration operation, as shown in FIG. 2C.
The link interface circuit 3 is not inputted with a command signal Q from an external link circuit to the end of the configuration operation. As a result, the command signal terminal TQ is in the low level and the instruction IS indicates xe2x80x9cno requestxe2x80x9d, as shown in FIG. 2F.
After completion of the configuration operation, the state S of the state machine 1 keeps staying in the xe2x80x9cidlexe2x80x9d state, waiting for a command signal to be inputted through the command signal terminal TQ from the external link circuit. Upon input of a transmission command signal from the command signal terminal TQ, the link interface circuit 3 outputs a xe2x80x9ctransmission requestxe2x80x9d instruction as an instruction IS to the state machine 1, as shown in FIG. 2F. Upon receipt of the xe2x80x9ctransmission requestxe2x80x9d instruction, the state machine 1 is changed to a xe2x80x9ctransmissionxe2x80x9d state to execute transmission operation, as shown in FIG. 2b. Then, the state machine 1 returns to the xe2x80x9cidlexe2x80x9d state. When the timer 2 counts a predetermined time after the return of the state machine 1 to the xe2x80x9cidlexe2x80x9d state, the state machine 1 outputs a pulse of the high level as the flag signal F, as shown in FIG. 2C.
As described above, the conventional communication LSI device does not operate after the end of the configuration operation unless a pattern signal (command signal) is inputted to the internal circuit of the LSI device is through the external command signal terminal TQ.
Also, in the closed test environment necessary for carrying out the dynamic bias temperature screening, even if the communication LSI device to be tested can be stored in a constant temperature vessel after the configuration operation, it is impossible to connect a pattern generator with the external terminal TQ of the LSI device to be tested to supply a test pattern. Therefore, a predetermined test cannot be carried out.
In conjunction with the above description, a single chip microcomputer is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-334463). In this reference, the single chip microcomputer is composed of a latch (207) which detects a standby transit instruction, and a selector 209 which selects the output of the latch (207) and an NMI (masking impossible interrupt) signal (115) based on a TEST signal (117) which sets the single chip microcomputer to a test mode. When the standby transit instruction is executed, the inner NMI signal 110 is generated to release the standby state. Even when the standby transit instruction is executed at the time of the test mode, a circuit is activated to cancel the standby state at the time of the dynamic bias temperature screening operation without input of the NMI signal or the RESET signal.
Also, a testing device of the semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-89996). In this reference, the testing device is composed of a multiphase clock generating circuit (4) and an input/output buffer circuits F/FA1 to F/FA10. The multiphase clock generating circuit (4) generates a scan mode signal SM, a normal clock signal CK for operating an internal logic, and a scan clock signal SCK for operating boundary scanning from s test terminal BT for the dynamic bias temperature screening method. The input/output buffer circuits F/FA1 to F/FA10 have a boundary scan test function. The Scan clock SCK is distributed to the input/output buffer circuits F/FA1 to F/FA10 and a normal clock is distributed to the input/output buffer circuits F/FA1 to F/FA10 and F/FB1 to F/FB10. The scan mode signal SM is connected to all the input/output buffer circuits F/FA1 to F/FA10 and F/FB1 to F/FB10 to switch between a scan mode and a normal mode. The output of the last stage F/FA10 of the boundary scanning is connected with the input of the first stage F/FA1, to form a boundary scanning loop. The single BT terminal allows static burn-in test to be carried out while operating the internal circuit.
Also, a microcomputer is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-3401). In this reference, when a dynamic bias temperature mode is set through a test terminal (7), a reset generating circuit (4) resets a microcomputer in response to not a reset signal 12 inputted from a reset terminal 6 but a test program end signal 10 which indicates that the execution of a program stored in a test ROM (3) is ended.
Therefore, an object of the present invention is to provide a communication LSI device which can automatically and repetitively carry out a test operation, and a test method of the same.
Also, another object of the present invention is to provide a communication LSI device which can automatically and repetitively detects a flag signal from a state machine and carry out a test operation in response to the flag signal, and a test method of the same.
In order to achieve an aspect of the present invention, a communication LSI device includes a state machine section and a test control section. The state machine section carries out a configuration operation in an idle state in response to a first reset signal. The state machine section changes to the idle state after completion of the configuration operation. The state machine section outputs a flag signal after a predetermined time since the state machine section changes to the idle state. The test control section outputs one the first reset signal to the state machine section in a test mode in response to the flag signal or a second reset signal externally supplied.
Here, the communication LSI device may further includes a link inter which outputs a first transmission command to the state machine section in response to a second transmission command externally supplied. In this case, the state machine section carries out a transmission operation in the idle state in response to the first transmission command, and then the state machine section changes to the idle state after completion of the configuration operation.
Also, the state machine section may include a timer. In this case, when the timer counts the predetermined time after the completion of the configuration operation, the state machine section outputs the flag signal in the idle state when the timer counts the predetermined time.
Also, the test control section may be set to the test mode in response to a test mode setting signal externally supplied.
Also, the second reset signal may be supplied to the test control section initially once.
In another aspect of the present invention, a method of testing a communication LSI device is attained by (a) setting a test mode; by (b) generating a first reset signal to a state machine section in an idle state in the test mode in response to a second reset signal externally supplied; by (c) carrying out a configuration operation by the state machine section in response to the first reset signal, wherein the state machine section changes to the idle state after completion of the configuration operation; by (d) generating a flag signal from the state machine section when the state machine section is in the idle state; by (e) generating a first transmission command in response to a second transmission command externally supplied; by (f) carrying out a transmission operation by the state machine section in the idle state in response to the first transmission command, wherein the state machine section changes to the idle state after completion of the transmission operation; and by (g) generating the first reset signal to the state machine section in the idle state in the test mode in response to the flag signal.
The state machine section may include a timer. In this case, the (d) generating may be attained by generating the flag signal in the idle state when the timer counts a predetermined time after the state machine section enters the idle state.
Also, the (a) setting may be attained by setting the test mode in response to a test mode setting signal externally supplied.
In order to achieve still another aspect of the present invention, a communication LSI device includes a state machine section, a resetting circuit, a test control section and a link interface section. The state machine section carries out a configuration operation in an idle state in response to a first reset signal, and then the state machine section changes to the idle state. Also, the state machine section carries out a transmission operation in the idle state in response to the first transmission command, and then the state machine section changes to the idle state. Further, the state machine section outputs a flag signal after a predetermined time since the state machine section changes to the idle state. The resetting circuit generates the first reset signal in response to a second reset signal externally supplied. The test control section outputs a second transmission command in a test mode in response to the flag signal. The link interface section outputs the first transmission command to the state machine section in response to the second transmission command.
Here, the state machine section may include a timer. In this case, when the timer counts a predetermined time after the state machine section enters the idle state, the state machine section outputs the flag signal in the idle state when the timer counts the predetermined time.
Also, the test control section may be set to the test mode in response to a test mode setting signal externally supplied.
Also, the third communication command reset signal may be supplied to the test control section initially once.
In yet still another aspect of the present invention, a method of testing a communication LSI device, is attained by (a) setting a test mode; by (b) generating a first reset signal to a state machine section in an idle state in the test mode in response to a second reset signal externally supplied; by (c) carrying out a configuration operation by the state machine section in response to the first reset signal, wherein the state machine section enters the idle state after completion of the configuration operation; by (d) generating a flag signal from the state machine section when the state machine section is in the idle state; by (e) generating a first transmission command in response to the flag signal; by (f) generating a second reset signal to the state machine section in the idle state in the test mode in response to the first transmission command; and by (g) carrying out a transmission operation by the state machine section in the idle state in response to the second transmission command, wherein the state machine section enters to the idle state after completion of the transmission operation.
Here, the state machine section may include a timer. The (d) generating may be attained by generating the flag signal in the idle state when the timer counts a predetermined time after the state machine section enters the idle state.
Also, the (a) setting may be attained setting the test mode in response to a test mode setting signal externally supplied.
Also, the method may further include generating the first transmission command in response to a third transmission command externally supplied.